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ABV

Assertion Based Verification (ABV) is a methodology employing assertions as the primary entry for verification, potentially both employing the assertions for simulation as well as formal property checking. ABV significantly improves the efficiency of the verification effort. Today the SystemVerilog Assertion language (SVA) is the state-of-art for employing ABV

CRV

Constrained Random Verification is a methodology that takes full advantage of verification environment automation and it dramatically reduces the time spent for creating test cases. Comparing this with the classical directed test creation approach, CRV significantly improves the RTL quality by easily hitting corner cases and finding unexpected bugs. The SystemVerilog methodologies VMM and OVM are today the industry standard for employing CRV.

VIP

Verification Interllectual Property (VIP) is a methodology for efficiently creating and reusing test bench structures aimed for CRV. Typically, SystemVerilog based VIP is implemented to be used with the VMM and OVM methodologies.

Verification Methodology

Verification methodologies are undergoing major changes. The time consuming task of writing directed tests is being replaced by more automated and constraint based methods centered around random verification. Methodologies like ABV and CRV are added as plug-ins to the existing industry approaches. It is important that such methodologies are scalable, predictable and manageable. To meet these goals, a well structured approach must be used for defining metrics on how the verification methodology is deployed. Such metrics combine and include structural and functional coverage, regression results, feature completion and resource utilization (people, machine licenses) to gain a fully optimized productive verification methodology. To implement these methodologies in a proper and reuse-able manner, SyoSil advices on how to build and incorporate different methodologies with minimal time effort.

The verification effort must be carried out in a highly productive manner. Directed approach do not cover unforeseen issues, but only covers bugs/issues with specific features. Constrained random verification is more robust, covers the unforeseen and has little impact of rework when the design architecture changes.

Efficiently employing coverage metrics is a part of adapting ABV and CRV, thus it is important to understand the importance of assertion functional and code coverage. The quality metric needed for determining when a design is ready for tape-out must be defined using these metrics.To perform efficient coverage driven verification, higher-level verification languages such as SystemVerilog/e/SystemC and methodologies like OVM/VMM must be employed.

SyoSil advises how to build VIP and tool flows that employ such languages and methodologies in combination with industry-leading EDA tools from various vendors. Design teams spending time and effort in adapting new technologies are more profitable and do enjoy faster time-to-market. SyoSil has long year expertise in advising and deploying industry proven verification methodology and in supporting the projects and teams from the architectural level to post-validation of an ASIC.

For more information related to the Verification Methodology and related services, please contact us with your request.

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